Next-generation wireless devices may use multi-core and/or parallel processing architectures to support the heightened signal processing requirements of Fifth Generation (5G) wireless network telecommunication protocols. In such architectures, memory resources may be shared by multiple central processing unit (CPU) elements (CEs) so that two or more CEs can simultaneously access the same memory resource. In this way, shared memory resources may provide an efficient means of passing data/messages between CEs that are executing different threads of an application. As used herein, the term “thread” refers to a sequence of programming instructions that is being executed by, or is otherwise scheduled for execution by, a single CE. In some instances, CEs executing different threads of an application may need to exchange data with one another in order to execute their respective threads. Shared memory provides an efficient means for passing data between CEs by allowing one CE to write data into a memory resource, and another CE to subsequently read the data from the memory resource. This is generally referred to as message passing.
Memory errors may occur when multiple CEs access the same shared memory resource if cache coherency is not maintained. More specifically, CEs will generally read data from a shared memory resource into a local cache of the CE, and then use the local copy of the data during execution of a corresponding thread. If another CE subsequently modifies the data stored in the shared memory resource via a write instruction, and then reads the modified data into its own cache, the local caches of the respective CEs will be inconsistent, meaning that cache coherency was not be maintained. Other scenarios, such as false sharing, may also affect cache coherency.